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BITMUX

General Form
BITMUX ( source_1, source_0, A0 ) (ASR)
BITMUX ( source_1, source_0, A0 ) (ASL)
Syntax
BITMUX ( Dreg , Dreg , A0 ) (ASR) ;
shifted out (b) */
BITMUX ( Dreg , Dreg , A0 ) (ASL) ;
shifted out (b) */
Syntax Terminology
:
Dreg
R7–0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Bit Multiplex instruction merges bit streams.
The instruction has two versions, Shift Right and Shift Left. This instruc-
tion overwrites the contents of
Table
13-4, and
In the Shift Right version, the processor performs the following sequence.
1. Right shift Accumulator
source_1
2. Right shift Accumulator
source_0
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
source_1
Table
13-5.
A0
into the MSB of the Accumulator.
A0
into the MSB of the Accumulator.
/* shift right, LSB is
/* shift left, MSB is
and
source_0
by one bit. Right shift the LSB of
by one bit. Right shift the LSB of
Bit Operations
. See
Table
13-3,
13-21

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