Analog Devices ADSP-BF53x Blackfin Reference page 811

Table C-7. Sample Opcode Holes Representation
Instruction
and Version
Zero Overhead Loop Setup
LOOP loop_name LC0
LOOP_BEGIN loop_name
LOOP_END loop_name
... is mapped to...
LSETUP ( pcrel5m2, pcrel11m2 ) LC0
... where the address of LOOP_BEGIN determines pcrel5m2, and the address of LOOP_END deter-
mines pcrel11m2.
Opcode Representation In Listings, Memory
Dumps
The Blackfin assembler produces opcodes in little endian format for mem-
ory storage. Little endian format is efficient for instruction fetching, but
not especially convenient for user readability. Each 16 bits of opcode are
stored in memory with the least significant byte first followed by the most
significant byte in the next higher address.
32-bit opcodes appear in memory as the most significant 16 bits first, fol-
lowed by the least significant 16 bits at the next higher address. The
reason is that the instruction length is encoded in the most significant 16
bits of the opcode. By storing this information in the lower addresses, the
Program Sequencer can determine in one fetch whether it can begin pro-
cessing the current instruction right away or must wait to fetch the
remainder of the instruction first.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xE080 0000— 1 1 1 0 0 0 0 0 1 0 0 0
0xE08F 03FF
0 0 0 0 0 0
Instruction Opcodes
Bin
pcrel5m2
divided by 2
pcrel11m2 divided by 2
C-11