Analog Devices ADSP-BF53x Blackfin Reference page 988

Instructions Listed By Operation Code
Table C-23. 32-Bit Opcode Instructions (Sheet 35 of 40)
Instruction
and Version
Byte Align
Dreg = ALIGN8 (Dreg, Dreg)
Byte Align
Dreg = ALIGN16 (Dreg, Dreg)
Byte Align
Dreg = ALIGN24 (Dreg, Dreg)
Arithmetic Shift
Dreg_lo = Dreg_lo >>> uimm4
Arithmetic Shift
Dreg_lo = Dreg_hi >>> uimm4
Arithmetic Shift
Dreg_hi = Dreg_lo >>> uimm4
Arithmetic Shift
Dreg_hi = Dreg_hi >>> uimm4
Arithmetic Shift
Dreg_lo = Dreg_lo << uimm4 (S)
Arithmetic Shift
Dreg_lo = Dreg_hi << uimm4 (S)
Arithmetic Shift
Dreg_hi = Dreg_lo << uimm4 (S)
Arithmetic Shift
Dreg_hi = Dreg_hi << uimm4 (S)
Logical Shift
Dreg_lo = Dreg_lo << uimm4
Logical Shift
Dreg_lo = Dreg_lo >> uimm4
Logical Shift
Dreg_lo = Dreg_hi << uimm4
Logical Shift
Dreg_lo = Dreg_hi >> uimm4
Logical Shift
Dreg_hi = Dreg_lo << uimm4
C-188 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
0xC60D 0000—
0xC60D 0E3F
0xC60D 4000—
0xC60D 4E3F
0xC60D 8000—
0xC60D 8E3F
0xC680 0180—
0xC680 0FFF
0xC680 1180—
0xC680 1FFF
0xC680 2180—
0xC680 2FFF
0xC680 3180—
0xC680 3FFF
0xC680 4000—
0xC680 4E7F
0xC680 5000—
0xC680 5E7F
0xC680 6000—
0xC680 6E7F
0xC680 7000—
0xC680 7E7F
0xC680 8000—
0xC680 8E7F
0xC680 8180—
0xC680 8FFF
0xC680 9000—
0xC680 9E7F
0xC680 9180—
0xC680 9FFF
0xC680 A000—
0xC680 AE7F