Table of Contents
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Instruction Overview
Functional Description
The Store Pointer Register instruction stores the contents of a 32-bit
P-register to a 32-bit memory location. The Pointer register is a P-register.
The indirect address and offset must yield an even multiple of 4 to main-
tain 4-byte word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
Options
The Store Pointer Register instruction supports the following options.
• Post-increment the destination pointer by 4 bytes.
• Post-decrement the destination pointer by 4 bytes.
• Offset the source pointer with a small (6-bit), word-aligned (multi-
ple of 4), unsigned constant.
• Offset the source pointer with a large (18-bit), word-aligned (mul-
tiple of 4), signed constant.
• Frame Pointer (
(multiple of 4), negative constant.
The indexed
FP
subroutine or function. Positive offsets relative to
arguments from a called function) can be accomplished using one of the
other versions of this instruction.
Stack Pointer.
Flags Affected
None
8-38
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) relative and offset with a 7-bit, word-aligned
FP
-relative form is typically used to access local variables in a
FP
includes the Frame Pointer and
Preg
(useful to access
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