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ITEST_COMMAND Register
When the Instruction Test Command register (
to, the L1 cache data or tag arrays are accessed, and the data is transferred
through the Instruction Test Data registers (
Instruction Test Command Register (ITEST_COMMAND)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 1300
WAYSEL[1:0] (Access Way)
00 - Access Way0
01 - Access Way1
10 - Access Way2
11 - Access Way3
(Address bits [11:10] in SRAM)
SET[4:0] (Set Index)
Selects one of 32 sets
(Address bits [9:5] in SRAM)
Figure 6-6. Instruction Test Command Register
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
ITEST_COMMAND
ITEST_DATA[1:0]
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Memory
) is written
).
Reset = 0x0000 0000
SBNK[1:0] (Subbank
Access)
00 - Access subbank 0
01 - Access subbank 1
10 - Access subbank 2
11 - Access subbank 3
(Address bits [13:12] in
SRAM)
RW (Read/Write Access)
0 - Read access
1 - Write access
TAGSELB (Array Access)
0 - Access tag array
1 - Access data array
DW[1:0] (Double Word
Index)
Selects one of four 64-bit
double words in a 256-bit
line (Address bits [4:3] in
SRAM)
6-21
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