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Instruction Overview
:
Dreg
R7–0
: 5-bit unsigned field that must be a multiple of 2, with a range of
uimm5m2
0 through 30 bytes
: 16-bit unsigned field that must be a multiple of 2, with a range
uimm16m2
of 0 through 65,534 bytes (0x0000 through 0xFFFE)
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length.
Functional Description
The Store Low Data Register Half instruction stores the least significant
16 bits of a 32-bit data register to a 16-bit memory location. The Pointer
register is either an I-register or a P-register.
The indirect address and offset must yield an even number to maintain
2-byte half-word address alignment. Failure to maintain proper alignment
causes an misaligned memory access exception.
The instruction versions that explicitly modify
optional circular buffering. See
on page 1-21
disable it prior to issuing this instruction by clearing the Length
Register (
Example: If you use
clear
L2
beforehand can result in unexpected Ireg values.
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.
8-50
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for more details. Unless circular buffering is desired,
) corresponding to the
Lreg
to increment your address pointer, first
I2
to disable circular buffering. Failure to explicitly clear
Ireg
"Automatic Circular Addressing"
used in this instruction.
Ireg
support
Lreg
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