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Memory Architecture
• Instruction and data cache options for microcontroller code, excel-
lent High Level Language (HLL) support, and ease of
programming cache control instructions, such as
FLUSH
• Memory protection
The L1 memories operate at the core clock frequency (
Overview of Scratchpad Data SRAM
The processor provides a dedicated 4K byte bank of scratchpad data
SRAM. The scratchpad is independent of the configuration of the other
L1 memory banks and cannot be configured as cache or targeted by DMA.
Typical applications use the scratchpad data memory where speed is criti-
cal. For example, the User and Supervisor stacks should be mapped to the
scratchpad memory for the fastest context switching during interrupt
handling.
The scratchpad data SRAM, like the other L1 blocks, operates at
core clock frequency (
performance. However, it cannot be accessed by the DMA
controller.
Overview of On-Chip Level 2 (L2) Memory
Some Blackfin derivatives feature a Level 2 (L2) memory on chip. The L2
memory provides low latency, high-bandwidth capacity. This memory sys-
tem is referred to as on-chip L2 because it forms an on-chip memory
hierarchy with L1 memory. On-chip L2 memory provides more capacity
than L1 memory, but the latency is higher. The on-chip L2 memory is
SRAM and can not be configured as cache. It is capable of storing both
instructions and data. The L1 caches can be configured to cache instruc-
tions and data located in the on-chip L2 memory. On-chip L2 memory
operates at
CCLK
6-4
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
). It can be accessed by the core at full
CCLK
frequency.
and
PREFETCH
).
CCLK
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