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Line Fill Buffer
As the new cache line is retrieved from external memory, each 64-bit word
is buffered in a four-entry line fill buffer before it is written to a 4K byte
memory bank within L1 memory. The line fill buffer allows the core to
access the data from the new cache line as the line is being retrieved from
external memory, rather than having to wait until the line has been writ-
ten into the cache. While the L1 port of the fill buffer is always 64 bits
wide, the width of port to external or L2 memory varies between
derivatives.
Cache Line Replacement
When the instruction memory unit is configured as cache, bits 9 through
5 of the instruction fetch address are used as the index to select the cache
set for the tag-address compare operation. If the tag-address compare
operation results in a cache miss, the Valid and LRU bits for the selected
set are examined by a cache line replacement unit to determine the entry
to use for the new cache line, that is, whether to use Way0, Way1, Way2,
or Way3. See
Figure 6-4, "Instruction Cache Organization Per Subbank,"
on page
6-12.
The cache line replacement unit first checks for invalid entries (that is,
entries having its Valid bit cleared). If only a single invalid entry is found,
that entry is selected for the new cache line. If multiple invalid entries are
found, the replacement entry for the new cache line is selected based on
the following priority:
• Way0 first
• Way1 next
• Way2 next
• Way3 last
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Memory
6-15
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