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: 6-bit unsigned field that must be a multiple of 4, with a range of
uimm6m4
0 through 60 bytes
: 7-bit unsigned field that must be a multiple of 4, with a range of
uimm7m4
4 through 128 bytes
: 17-bit unsigned field that must be a multiple of 4, with a range
uimm17m4
of 0 through 131,068 bytes (0x0000 0000 through 0x0001 FFFC)
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length.
Functional Description
The Load Data Register instruction loads a 32-bit word into a 32-bit
D-register from a memory location. The Source Pointer register can be a
P-register, I-register, or the Frame Pointer.
The indirect address and offset must yield an even multiple of 4 to main-
tain 4-byte word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
The instruction versions that explicitly modify
optional circular buffering. See
on page 1-21
disable it prior to issuing this instruction by clearing the Length
Register (
Example: If you use
clear
L2
beforehand can result in unexpected Ireg values.
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for more details. Unless circular buffering is desired,
) corresponding to the
Lreg
to increment your address pointer, first
I2
to disable circular buffering. Failure to explicitly clear
Ireg
"Automatic Circular Addressing"
used in this instruction.
Ireg
Load / Store
support
Lreg
8-11
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