Byteop16M (Quad 8-Bit Subtract) - Analog Devices ADSP-BF53x Blackfin Reference

Instruction Overview

BYTEOP16M (Quad 8-Bit Subtract)

General Form
(dest_reg_1, dest_reg_0) = BYTEOP16M (src_reg_0, src_reg_1)
(dest_reg_1, dest_reg_0) = BYTEOP16M (src_reg_0, src_reg_1) (R)
Syntax
/* forward byte order operands */
(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair) ;
/* reverse byte order operands */
(Dreg, Dreg) = BYTEOP16M (Dreg-pair, Dreg-pair) (R) ; /* (b) */
Syntax Terminology
:
Dreg R7–0
:
Dreg_pair R1:0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Quad 8-Bit Subtract instruction subtracts two unsigned quad byte
number sets byte wise, adjusting for byte alignment. The instruction loads
the byte-wise results as sign-extended half-words in two destination regis-
ters, as shown in
Table 18-24. Source Registers Contain
aligned_src_reg_0:
aligned_src_reg_1:
18-32 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, , only
R3:2
Table 18-24 and
31................24 23................16
y3
z3
Table 18-25.
15..................8
y2 y1
z2 z1
/* (b */)
7....................0
y0
z0