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Table C-17. Arithmetic Operations Instructions (Sheet 9 of 44)
Instruction
and Version
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (IU)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (T)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (TFU)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (S2RND)
Multiply 16-Bit Operands
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (ISS2)
Multiply 16-Bit Operands
NOTE: When issuing compatible load/store instructions in parallel with a Multiply 16-Bit Operands
instruction, add 0x0800 0000 to the Multiply 16-Bit Operands opcode.
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi (IH)
Multiply 16-Bit Operands
Dreg_even = Dreg_lo_hi * Dreg_lo_hi
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC380 2000—
1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0
0xC380 27FF
0 0 1 0 0 Dreg
0xC240 2000—
1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0
0xC240 27FF
0 0 1 0 0 Dreg
0xC2C0 2000—
1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0
0xC2C0 27FF
0 0 1 0 0 Dreg
0xC220 2000—
1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0
0xC220 27FF
0 0 1 0 0 Dreg
0xC320 200—
1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0
0xC320 27FF0
0 0 1 0 0 Dreg
0xC360 2000—
1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0
0xC360 27FF
0 0 1 0 0 Dreg
0xC208 2000—
1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0
0xC208 27FF
0 0 1 0 0 Dreg
Instruction Opcodes
Bin
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
Dest.
src_reg_
half
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-63
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