Analog Devices ADSP-BF53x Blackfin Reference page 878

Arithmetic Operations Instructions
Table C-17. Arithmetic Operations Instructions (Sheet 24 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 – = Dreg_lo_hi * Dreg_lo_hi) (S2RND)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 – = Dreg_lo_hi * Dreg_lo_hi) (ISS2)
Multiply and Multiply-Accumulate
to Half Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_lo = (A0 – = Dreg_lo_hi * Dreg_lo_hi) (IH)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (FU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (IS)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (IU)
C-78 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC023 3000— 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1
0xC023 37FF
0 0 1 1 0 Dreg
0xC123 3000— 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1
0xC123 37FF
0 0 1 1 0 Dreg
0xC163 3000— 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1
0xC163 37FF
0 0 1 1 0 Dreg
0xC004 1800— 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0xC004 D9FF
Dreg
half
0xC084 1800— 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0
0xC084 D9FF
Dreg
half
0xC104 1800— 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0
0xC104 D9FF
Dreg
half
0xC184 1800— 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0
0xC184 D9FF
Dreg
half
Bin
Dest.
half Dreg #
Dest.
half Dreg #
Dest.
half Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #