Analog Devices ADSP-BF53x Blackfin Reference page 240

L1 Instruction Memory
32-BIT IAB ADDRESS
FOR LOOKUP
31 14
1
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
LINE
SELECT
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
Figure 6-4. Instruction Cache Organization Per Subbank
6-12 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
SUBBANK
SELECT
13 12 11 10 9
ADDRESS TAG
2+1 20
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
1 2+1 20
. . .
WD3 WD2 WD1 WD0
WD3
WD3 WD2 WD1 WD0
WD3
WD3
WD3
1 2+1 20
. . .
WD3
VALID LRU ADDRESS
WD3
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
1 2+1 20
. . .
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
VALID LRU ADDRESS
. . .
VALID LRU ADDRESS
VALID LRU ADDRESS
BYTE
SELECT
5 4 0
WAY 3
4 x 64
LINE 0
LINE 1
LINE 2
WAY 2
LINE 3
4 x 64
. . .
LINE 30
WD2 WD1 WD0
LINE 0
LINE 31
WD2 WD1 WD0
LINE 1
WD2 WD1 WD0
LINE 2
WAY 1
WD2 WD1 WD0
LINE 3
4 x 64
. . .
WD2 WD1 WD0
LINE 30
WD3 WD2 WD1 WD0
LINE 0
WD2 WD1 WD0
LINE 31
WD3 WD2 WD1 WD0
LINE 1
WD3 WD2 WD1 WD0
LINE 2
WD3 WD2 WD1 WD0
LINE 3
4 x 64
. . .
WD3 WD2 WD1 WD0
LINE 30
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
LINE 31
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
. . .
WD3 WD2 WD1 WD0
WD3 WD2 WD1 WD0
IDB DATA
4:1 MUX
WAY 0
LINE 0
LINE 1
LINE 2
LINE 3
LINE 30
LINE 31
64-BIT