Analog Devices ADSP-BF53x Blackfin Reference page 556

Instruction Overview
: Optionally
opt_mode_2
used with MAC1 versions either alone or with any of these other options.
When used together, the option flags must be enclosed in one set of
parenthesis and separated by a comma. Example:
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Multiply 16-Bit Operands instruction multiplies the two 16-bit oper-
ands and stores the result directly into the destination register with
saturation.
The instruction is like the Multiply-Accumulate instructions, except that
Multiply 16-Bit Operands does not affect the Accumulators.
Operations performed by the Multiply-and-Accumulate Unit 0 (MAC0)
portion of the architecture load their 16-bit results into the lower half of
the destination data register; 32-bit results go into an even numbered
. Operations performed by MAC1 load their results into the upper
Dreg
half of the destination data register or an odd numbered
In 32-bit result syntax, the MAC performing the operation will be deter-
mined by the destination Dreg. Even-numbered
invoke MAC0. Odd-numbered
Therefore, 32-bit result operations using the (
formed on odd-numbered Dreg destinations.
In 16-bit result syntax, the MAC performing the operation will be deter-
mined by the destination
MAC0. High-half
operations using the (
destinations.
15-44 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, , or
(FU) (IS)
Dregs
half. Low-half
Dreg
( ) invoke MAC1. Therefore, 16-bit result
Dregs R7–0.H
) option can only be performed on high-half
M
. Optionally,
(ISS2)
(M, IS)
(
Dregs R6
( , , , ) invoke MAC1.
R7 R5 R3 R1
) option can only be per-
M
(
Dregs R7–0.L
can be
(M)
.
Dreg
, , )
R4 R2, R0
) invoke
Dreg