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Instruction Overview
Result is 16-bit half D-register
r2.h=(a1=r7.l*r6.h), r2.l=(a0=r7.h*r6.h) ;
and MAC1 execution, both are signed fractions, both products load
into the Accumulators,MAC1 into half-word registers. */
r4.l=(a0=r1.l*r0.l), r4.h=(a1+=r1.h*r0.h) ;
but sum result into A1. ; MAC order is arbitrary. */
r7.h=(a1+=r6.h*r5.l), r7.l=(a0=r6.h*r5.h) ;
subtract into A0
r0.h=(a1=r7.h*r4.l) (m), r0.l=(a0+=r7.l*r4.l) ;
plies a signed fraction by an unsigned fraction. MAC0 multiplies
two signed fractions. */
r5.h=(a1=r3.h*r2.h) (m), r5.l=(a0+=r3.l*r2.l) (fu) ;
multiplies signed fraction by unsigned fraction. MAC0 multiplies
two unsigned fractions. */
r0.h=(a1+=r3.h*r2.h), r0.l=(a0=r3.l*r2.l) (is) ;
perform signed integer multiplication. */
r5.h=(a1=r2.h*r1.h), a0+=r2.l*r1.l ;
signed fractions. MAC0 does not copy the accum result. */
r3.h=(a1=r2.h*r1.h) (m), a0=r2.l*r1.l ;
signed fraction by unsigned fraction and uses all 40 bits of A1.
MAC0 multiplies two signed fractions. */
r3.h=a1, r3.l=(a0+=r0.l*r1.l) (s2rnd) ;
lator to register half. MAC0 multiplies signed fractions. Both
scale the result and round on the way to the destination regis-
ter. */
r0.l=(a0+=r7.l*r6.l), r0.h=(a1+=r7.h*r6.h) (iss2) ;
MACs process signed integer the way to the destination half-reg-
isters. */
19-44
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
*/
/* simultaneous MAC0
/* same as above,
/* sum into A1,
/* MAC1 multi-
/* both MACs
/* both MACs multiply
/* MAC1 multiplies
/* MAC1 copies Accumu-
/* both
/* MAC1
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