Analog Devices ADSP-BF53x Blackfin Reference page 886

Arithmetic Operations Instructions
Table C-17. Arithmetic Operations Instructions (Sheet 32 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (IH, M)
Multiply and Multiply-Accumulate to Half Register
LEGEND:
Dreg half determines which halves of the input oper-
and registers to use.
Dreg_lo * Dreg_lo
Dreg_lo * Dreg_hi
Dreg_hi * Dreg_lo
Dreg_hi * Dreg_hi
Dest. Dreg # encodes the destination Data Register.
src_reg_0 Dreg # encodes the input operand register to the left of the "*" operand.
src_reg_1 Dreg # encodes the input operand register to the right of the "*" operand.
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Multiply and Multiply-Accumulate
to Data Register
Dreg_even = (A0 = Dreg_lo_hi * Dreg_lo_hi)
Multiply and Multiply-Accumulate
to Data Register
Dreg_even = (A0 = Dreg_lo_hi * Dreg_lo_hi) (FU)
C-86 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC176 1800— 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0
0xC176 D9FF
Dreg
half
Dreg
half
0 0
0 1
1 0
1 1
0xC00D 0000— 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1
0xC00D 07FF
0 0 0 0 0 Dreg
0xC08D 0000— 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1
0xC08D 07FF
0 0 0 0 0 Dreg
Bin
0 1 1 0 0 Dest.
Dreg #
Dest.
half Dreg #
Dest.
half Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #