Analog Devices ADSP-BF53x Blackfin Reference page 237

Table of Contents

Advertisement

CACHE CONTROL &
MEMORY MANAGEMENT
CACHE
CACHE
INSTRUCTION DATA BUS (IDB)
REGISTER ACCESS BUS (RAB)
Figure 6-3. L1 Instruction Memory Bank Architecture
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
CACHE
TAG
TAG
4 KB
4 KB
64
4 KB
4 KB
CACHE
TAG
TAG
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
TO DMA CONTROLLER
TO EBIU (AND L2)
HIGH PRIORITY
LOW PRIORITY
LINE FILL
LINE FILL
BUFFER
BUFFER
8 X 32 BIT
8 X 32 BIT
64
The shaded blocks are not
present on all derivatives.
For more information,
please refer to the
corresponding hardware
reference.
4 KB
64
4 KB
4 KB
64
4 KB
DMA CORE BUS (DCB)
EXTERNAL ACCESS BUS (EAB)
64
TO
PROCESSOR
32
CORE
Memory
DMA
BUFFER
DMA
BUFFER
DMA
BUFFER
16
16
6-9

Advertisement

Table of Contents
loading

This manual is also suitable for:

Adsp-bf56x blackfin

Table of Contents