Analog Devices ADSP-BF53x Blackfin Reference page 730

Instruction Overview
• The destination D-registers (if applicable) for both scalar opera-
tions must form a vector couplet, as described below.
• 16-bit: store the results in the upper- and lower-halves of
the same 32-bit
MAC1 writes to the upper half.
• 32-bit: store the results in valid
the pair's lower (even-numbered)
the upper (odd-numbered)
Valid pairs are
Dreg
Syntax
Separate the two compatible scalar instructions with a comma to produce
a vector instruction. Add a semicolon to the end of the combined instruc-
tion, as usual. The order of the MAC operations on the command line is
arbitrary.
Instruction Length
This instruction is 32 bits long.
Flags Affected
The flags reflect the results of the two scalar operations.This instruction
affects flags as follows.
• is set if any result extracted to a
V
saturate.
• is set if
VS
• is set if result in Accumulator
AV0
cleared if
• is set if
AV0S
19-42 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Dreg
, ,
R7:6 R5:4 R3:2
is set; unaffected otherwise.
V
result does not saturate.
A0
is set; unaffected otherwise.
AV0
. MAC0 writes to the lower half, and
pairs. MAC0 writes to
Dreg
, and MAC1 writes to
Dreg
.
Dreg
, and .
R1:0
saturates; cleared if no
Dreg
(MAC0 operation) saturates;
A0
Dregs