Analog Devices ADSP-BF53x Blackfin Reference page 802

Introduction
Glossary
The following terms appear throughout this document. Without trying to
explain the Blackfin architecture, here are the terms used with their defini-
tions. See chapters 1 through 6 for more details on the architecture.
Register Names
The architecture includes the following registers.
Table C-1. Registers
Register
Accumulators
Data Registers
Pointer Registers
Stack Pointer
Frame Pointer
Loop Top
Loop Count
Loop Bottom
C-2 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
The set of 40-bit registers A1 and A0 that normally contain data that is being
manipulated. Each Accumulator can be accessed in five ways—as one 40-bit
register, as one 32-bit register (designated as A1.W or A0.W), as two 16-bit
registers similar to Data registers (designated as A1.H, A1.L, A0.H, or A0.L)
and as one 8-bit register (designated A1.X or A0.X) for the bits that extend
beyond bit 31.
The set of 32-bit registers R0, R1, ..., R6, R7 that normally contain data for
manipulation. Abbreviated D-register or Dreg. Data registers can be accessed
as 32-bit registers, or optionally as two independent 16-bit registers. The least
significant 16 bits of each register is called the "low" half and is designated
with ".L" following the register name. The most significant 16-bit is called the
"high" half and is designated with ".H" following the name. Example: R7.L,
r2.h, r4.L, R0.h.
The set of 32-bit registers P0, P1, ..., P4, P5, including SP and FP that nor-
mally contain byte addresses of data structures. Accessed only as a 32-bit regis-
ter. Abbreviated P-register or Preg. Example: p2, p5, fp, sp.
SP; contains the 32-bit address of the last occupied byte location in the stack.
The stack grows by decrementing the Stack Pointer. A subset of the Pointer
Registers.
FP; contains the 32-bit address of the previous Frame Pointer in the stack,
located at the top of a frame. A subset of the Pointer Registers.
LT0 and LT1; contains 32-bit address of the top of a zero overhead loop.
LC0 and LC1; contains 32-bit counter of the zero overhead loop executions.
LB0 and LB1; contains 32-bit address of the bottom of a zero overhead loop.