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Core Interrupt Mask Register (IMASK)
For all bits, 0 - Interrupt masked, 1 - Interrupt enabled
0xFFE0 2104
15 14 13 12 11 10
IVG15
IVG14
IVG13
IVG12
IVG11
IVG10
Figure 4-5. Core Interrupt Mask Register
ILAT Register
Each bit in the Core Interrupt Latch register (
responding event is latched, but not yet accepted into the processor (see
Figure
4-6). The bit is reset before the first instruction in the correspond-
ing ISR is executed. At the point the interrupt is accepted,
cleared and
IPEND[N]
read in Supervisor mode. Writes to
Supervisor mode). To clear bit
IMASK[N] == 0
is provided for cases where latched interrupt requests need to be
ILAT
cleared (cancelled) instead of serviced.
The
instruction can be used to set
RAISE
also
or
ILAT[2]
Only the JTAG
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
9
8
0
0
0
0
0
0
0
0
will be set simultaneously. The
N
, and then write
ILAT[N] = 1
.
ILAT[1]
pin can clear
TRST
Program Sequencer
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
1
1
1
1
) indicates that the cor-
ILAT
are used to clear bits only (in
ILAT
from
, first make sure that
ILAT
. This write functionality to
ILAT[15]
.
ILAT[0]
0
Reset = 0x0000 001F
0
1
IVHW (Hardware Error)
IVTMR (Core Timer)
IVG7
IVG8
IVG9
will be
ILAT[N]
register can be
ILAT
through
, and
ILAT[5]
4-39
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