Analog Devices ADSP-BF53x Blackfin Reference page 661

The relationship between the I-register bits and the byte alignment is
illustrated below.
In the default source order case (for example, not the (R) syntax), assume a
source register pair contains the data shown in
Table 18-13. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Options
The Quad 8-Bit Average – Byte instruction supports the following
options.
Table 18-14. Options for Quad 8-Bit Average – Byte
Option
Default
(T)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
src_reg_pair_HI
byte7 byte6 byte5
byte5
byte6 byte5
Description
Rounds up the arithmetic mean.
Truncates the arithmetic mean.
Video Pixel Operations
Table 18-13.
src_reg_pair_LO
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
byte1 byte0
byte1 byte0
byte1
18-21