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Instruction Overview
Table 18-7. Source Registers Contain
aligned_src_reg_0:
aligned_src_reg_1:
Table 18-8. Destination Registers Receive
aligned_src_reg_0:
aligned_src_reg_1:
The Quad 8-Bit Add instruction provides byte alignment directly in the
source register pairs
and
.
I1
• The two LSBs of the
source register pair
• The two LSBs of the
source register pair
The relationship between the I-register bits and the byte alignment is
illustrated below.
In the default source order case (for example, not the (R) syntax), assume
that a source register pair contains the data shown in
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Options
The (R) syntax reverses the order of the source registers within each regis-
ter pair. Typical high performance applications cannot afford the
overhead of reloading both register pair operands to maintain byte order
18-16
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31................24
23................16
y3
z3
31................24
23................16
y1 + z1
y3 + z3
and
src_reg_0
register determine the byte alignment for
I0
src_reg_0
register determine the byte alignment for
I1
src_reg_1
15..................8
y2
y1
z2
z1
15..................8
based on index registers
src_reg_1
(typically
).
R1:0
(typically
).
R3:2
Table
7....................0
y0
z0
7....................0
y0 + z0
y2 + z2
I0
18-9.
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