Analog Devices ADSP-BF53x Blackfin Reference page 1024

Index
LRUPRIORST (LRU priority reset) bit,
6-5, 6-7
LSETUP (loop setup) instruction, 4-22,
7-13
LSHIFT...BY instruction, 14-14,
LSHIFT (logical shift) instruction, 2-48,
14-14
LT (loop top) register, 1-13, 4-22,
M
MAC (multiplier-accumulator),
2-48
See also multiply without accumulate
A0, A1, 2-46
capabilities, 1-3
combining MAC0 and MAC1
operations in vector instructions,
19-41
defined, 1-14
description summary,
dual operations, 2-47
dual operations example,
mixed mode option (M), 15-43, 15-48,
15-55, 15-64, 15-70, 19-38,
multicycle 32-bit instruction,
major architectural change[7:0] field,
21-27
manual, conventions, xxxvi
mapping multiple interrupt sources,
maximum instruction,
maximum instructions
maximum, 15-30, C-60
vector maximum, 19-32,
MAX (vector maximum) instruction,
15-30, 19-32
media access control, See MAC
I-22 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
19-28
4-24
2-35 to
C-3
2-47
19-41
2-46
4-55
C-60
C-115
memory
See also cache; level 1 (L1) memory; level
1 (L1) data memory; level 1 (L1)
instruction memory; level 2 (L2)
memory
access limit, 1-5
address alignment, 5-16
architecture, 6-2 to 6-4
architecture of, 1-4
DMA controller, 1-5
external, 1-6
instruction storage, 6-65
internal, 1-5
L1 data, 6-24 to 6-38
level 2 (L2), 6-43
management, 6-45
nonaligned operations,
off-chip, 1-5, 1-6
page descriptor table,
pages, 6-48
protected, 3-5
protected regions, 6-54
protection and properties,
protection between tasks,
protection in user mode,
terminology, 6-74 to
transaction model, 6-65
memory management unit. See MMU
memory-mapped register. See MMR
memory pages, 6-48
minimum instructions,
minimum, 15-32, C-61
vector minimum, C-115
minimum (MIN) instruction,
vector minimum, 19-35
MIN (vector minimum) instruction,
15-32, 19-35
mixed mode option (M), 15-43, 15-48,
15-55, 15-64, 15-70
mixed-multiply mode,
6-71
6-50
6-45 to 6-63
6-52
6-53
6-76
C-61
15-32
2-41