Analog Devices ADSP-BF53x Blackfin Reference page 559

Table 15-2. Multiply 16-Bit Operands Options (Cont'd)
Option Description for
Register Half Destination
(T) Signed fraction with truncation. Trun-
cate Accumulator 9.31 format value at
bit 16. (Perform no rounding.) Satu-
rate the result to 1.15 precision in desti-
nation register half. Result is between
minimum -1 and maximum 1-2
expressed in hex, between minimum
0x8000 and maximum 0x7FFF).
(TFU) Unsigned fraction with truncation.
Multiply 1.15 * 1.15 to produce 1.31
results after left-shift correction. (Iden-
tical to Default.) Truncate 1.32 format
value at bit 16. (Perform no rounding.)
Saturate the result to 0.16 precision in
destination register half. Result is
between minimum 0 and maximum
-16
1-2
minimum 0x0000 and maximum
0xFFFF).
(S2RND) Signed fraction with scaling and round-
ing. Multiply 1.15 * 1.15 to produce
1.31 results after left-shift correction.
(Identical to Default.) Shift the result
one place to the left (multiply x 2).
Round 1.31 format value at bit 16.
(RND_MOD bit in the ASTAT register
controls the rounding.) Saturate the
result to 1.15 precision in destination
register half. Result is between mini-
mum -1 and maximum 1-2
expressed in hex, between minimum
0x8000 and maximum 0x7FFF).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(or, expressed in hex, between
-15
(or,
Arithmetic Operations
Description for
32-Bit Register Destination
Not applicable. Truncation is meaning-
less for 32-bit register destinations.
-15
(or,
Not applicable.
Not applicable.
15-47