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contain the same register information, giving the options for squaring and
multiplying the high half and low half of the same register.
show these possible combinations.
A
31
39
C
31
39
Figure 2-11. Four Possible Combinations of MAC Operations
The 32-bit product is passed to a 40-bit adder/subtracter, which may add
or subtract the new product from the contents of the Accumulator Result
register or pass the new product directly to the Data Register File Results
register. For results, the
registers consists of smaller 32- and 8-bit registers—
.
A1.X
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
B
Rm
Rp
MAC0
A0
D
Rm
Rp
MAC0
A0
and
registers are 40 bits wide. Each of these
A0
A1
Computational Units
Figure 2-11
31
Rm
Rp
MAC0
39
A0
31
Rm
Rp
MAC0
39
A0
,
A0.W
A1.W
,
and
A0.X,
2-43
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