Analog Devices ADSP-BF53x Blackfin Reference page 551

See "Rounding and Truncating" on page 1-19
ing behavior.
The instruction versions that explicitly modify
optional circular buffering. See
on page 1-21
disable it prior to issuing this instruction by clearing the Length
Register (
Example: If you use
clear
L2
beforehand can result in unexpected
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.
Options
–bit reverse carry adder. When specified, the carry bit is propagated
(BREV)
from left to right, as shown in
When bit reversal is used on the Index Register version of this instruction,
circular buffering is disabled to support operand addressing for FFT,
DCT and DFT algorithms. The Pointer Register version does not support
circular buffering in any case.
Table 15-1. Bit Addition Flow for the Bit Reverse (BREV) Case
an
| cn
+
|
bn
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for more details. Unless circular buffering is desired,
) corresponding to the
Lreg
to increment your address pointer, first
I2
to disable circular buffering. Failure to explicitly clear
Figure
a2 a1
| c2 |
+ +
| |
b2 b1
Arithmetic Operations
for a description of round-
Ireg
"Automatic Circular Addressing"
used in this instruction.
Ireg
values.
Ireg
15-1, instead of right to left.
a0
c1 |
+
|
b0
support
Lreg
c0
15-39