Analog Devices ADSP-BF53x Blackfin Reference page 665

Syntax Terminology
:
Dreg R7–0
:
Dreg_pair R1:0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Quad 8-Bit Average – Half-Word instruction finds the arithmetic
average of two unsigned quad byte number sets byte wise, adjusting for
byte alignment. This instruction averages four bytes together. The instruc-
tion loads the results as bytes on half-word boundaries in one 32-bit
destination register. Some syntax options load the upper byte in the
half-word and others load the lower byte, as shown in
Table 18-17, and
Table 18-16. Source Registers Contain
aligned_src_reg_0:
aligned_src_reg_1:
Table 18-17. The versions that load the result into the lower byte – RNDL
and TL – produce:
dest_reg:
In either case, the unused bytes in the destination register are filled with
0x00.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, , only
R3:2
Table 18-18.
31................24 23................16
y3
z3
31................24 23................16
0 . . . . . . 0 avg(y3, y2, z3,
Video Pixel Operations
15..................8
y2 y1
z2 z1
15..................8
0 . . . . . . 0
z2)
Table 18-16,
7....................0
y0
z0
7....................0
avg(y1, y0, z1,
z0)
18-25