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Program Sequencer
The fetched address enters the instruction pipeline, ending with the pro-
gram counter (
). The pipeline contains the 32-bit addresses of the
PC
instructions currently being fetched, decoded, and executed. The
cou-
PC
ples with the
registers, which store return addresses. All addresses
RETn
generated by the sequencer are 32-bit memory instruction addresses.
To manage events, the event controller handles interrupt and event pro-
cessing, determines whether an interrupt is masked, and generates the
appropriate event vector address.
In addition to providing data addresses, the data address generators
(DAGs) can provide instruction addresses for the sequencer's indirect
branches.
The sequencer evaluates conditional instructions and loop termination
conditions. The loop registers support nested loops. The memory-mapped
registers (MMRs) store information used to implement interrupt service
routines.
Figure 4-2
shows the core Program Sequencer module and how it inter-
connects with the Core Event Controller and the System Event
Controller.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-3
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