Dual 16-Bit Accumulator Extraction With Addition - Analog Devices ADSP-BF53x Blackfin Reference

Dual 16-Bit Accumulator Extraction with Addition

General Form
dest_reg_1 = A1.L + A1.H, dest_reg_0 = A0.L + A0.H
Syntax
Dreg = A1.L + A1.H, Dreg = A0.L + A0.H ;
Syntax Terminology
:
Dreg R7–0
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Dual 16-Bit Accumulator Extraction with Addition instruction adds
together the upper half-words (bits 31through 16) and lower half-words
(bits 15 through 0) of each Accumulator and loads each result into a
32-bit destination register.
Each 16-bit half-word in each Accumulator is sign extended before being
added together.
Flags Affected
None
Required Mode
User & Supervisor
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Video Pixel Operations
/* (b) */
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