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In the preceding example code, the
• The conditional branch (
forcing stalls into the execution pipeline until the condition is
resolved and any entries in the processor store buffer have been
flushed.
• All pending interrupts or exceptions have been processed before
completes.
CSYNC
• The load is not fetched from memory speculatively.
The
instruction ensures that all side effects of previous operations
SSYNC
are propagated out through the interface between the L1 memories and
the rest of the chip. In addition to performing the core synchronization
functions of
CSYNC
between the L1 memory and the system domain and generates a sync
request to the system that requires acknowledgement before
completes.
Speculative Load Execution
Load operations from memory do not change the state of the memory
value. Consequently, issuing a speculative memory-read operation for a
subsequent load instruction usually has no undesirable side effect. In some
code sequences, such as a conditional branch instruction followed by a
load, performance may be improved by speculatively issuing the read
request to the memory system before the conditional branch is resolved.
For example,
away_from_here:
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
IF CC JUMP away_from_here
, the
instruction flushes any write buffers
SSYNC
IF CC JUMP away_from_here
RO = [P2];
...
instruction ensures:
CSYNC
Memory
) is resolved,
SSYNC
6-69
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