Analog Devices ADSP-BF53x Blackfin Reference page 893

Table C-17. Arithmetic Operations Instructions (Sheet 39 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (S2RND, M)
Multiply and Multiply-Accumulate
to Data Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_odd = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (ISS2, M)
Multiply and Multiply-Accumulate to Data Register
LEGEND: Dreg half determines which halves of the
input operand registers to use.
Dreg_lo * Dreg_lo
Dreg_lo * Dreg_hi
Dreg_hi * Dreg_lo
Dreg_hi * Dreg_hi
Dest. Dreg # encodes the destination Data Register.
src_reg_0 Dreg # encodes the input operand register to the left of the "*" operand.
src_reg_1 Dreg # encodes the input operand register to the right of the "*" operand.
Negate (Two's-Complement)
Dreg = – Dreg
Negate (Two's-Complement)
Dreg = – Dreg (NS)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC03A 1800— 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0
0xC03A D9FF
Dreg
half
0xC13A 1800— 1 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0
0xC13A D9FF
Dreg
half
Dreg
half
0 0
0 1
1 0
1 1
0x4380— 0 1 0 0 0 0 1 1 1 0 Source
0x43BF
0xC407 C000— 1 1 0 0 0 1 0 x x x 0 0 0 1 1 1
0xC407 CFC0
1 1 0 0 Dest.
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 0 0 Source
Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
Dest.
Dreg # Dreg #
0 0 0
Dreg #
C-93