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L1 Data Memory
when posted writes are to a slow external memory device. When returning
from a high priority interrupt service routine to a low priority interrupt
service routine or user mode, the core stalls until the write buffer has com-
pleted the necessary writes to return to a two-deep state. By default, the
write buffer is a fixed two-deep FIFO.
Interrupt Priority Register (IPRIO)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 2110
0
0
15 14 13 12 11 10
0
0
Figure 6-12. Interrupt Priority Register
6-36
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
0
0
0
0
0
0
0
0
9
8
7
6
0
0
0
0
0
0
0
0
Reset = 0x0000 0000
0
0
0
0
0
0
5
4
3
2
1
0
0
0
0
0
0
0
IPRIO_MARK[0:3] (Priority
Watermark)
0000 - Default, all interrupts
0001 - Interrupts 15 through 1
0010 - Interrupts 15 through 2
...
1110 - Interrupts 15 and 14
1111 - Interrupt 15 is low
are low priority
are low priority, interrupt
0 is considered high
priority
are low priority,
interrupts 1 and 0 are
considered high priority
are low priority,
interrupts 13 through 0
are considered high
priority
priority, all others are
considered high priority
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