Analog Devices ADSP-BF53x Blackfin Reference page 41

Introduction
Each MAC can perform a 16- by 16-bit multiply per cycle, with accumu-
lation to a 40-bit result. Signed and unsigned formats, rounding, and
saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations
on 16-bit or 32-bit data. Many special instructions are included to acceler-
ate various signal processing tasks. These include bit operations such as
32
field extract and population count, modulo 2 multiply, divide primi-
tives, saturation and rounding, and sign/exponent detection. The set of
video instructions include byte alignment and packing operations, 16-bit
and 8-bit adds with clipping, 8-bit average operations, and 8-bit sub-
tract/absolute value/accumulate (SAA) operations. Also provided are the
compare/select and vector search instructions. For some instructions, two
16-bit ALU operations can be performed simultaneously on register pairs
(a 16-bit high half and 16-bit low half of a compute register). By also
using the second ALU, quad 16-bit operations are possible.
The 40-bit shifter can deposit data and perform shifting, rotating, normal-
ization, and extraction operations.
A program sequencer controls the instruction execution flow, including
instruction alignment and decoding. For program flow control, the
sequencer supports PC-relative and indirect conditional jumps (with static
branch prediction) and subroutine calls. Hardware is provided to support
zero-overhead looping. The architecture is fully interlocked, meaning
there are no visible pipeline effects when executing instructions with data
dependencies.
The address arithmetic unit provides two addresses for simultaneous dual
fetches from memory. It contains a multiported register file consisting of
four sets of 32-bit Index, Modify, Length, and Base registers (for circular
buffering) and eight additional 32-bit pointer registers (for C-style
indexed stack manipulation).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference 1-3