Analog Devices ADSP-BF53x Blackfin Reference page 776

Cycle Counter
The cycle counter is 64 bits and increments every cycle. The count value is
stored in two 32-bit registers,
bits (LSBs) are stored in
stored in
CYCLES2
To ensure read coherency, a read of
CYCLES2
CYCLES2
only updated on another read from
In User mode, these two registers may be read, but not written. In Super-
visor and Emulator modes, they are read/write registers.
To enable the cycle counters, set the
following example shows how to use the cycle counter:
R2 = 0;
CYCLES = R2;
CYCLES2 = R2;
R2 = SYSCFG;
BITSET(R2,1);
SYSCFG = R2;
/* Insert code to be benchmarked here. */
R2 = SYSCFG;
BITCLR(R2,1);
SYSCFG = R2;
CYCLES and CYCLES2 Registers
The Execution Cycle Count registers (
Figure 21-14. This 64-bit counter increments every
register contains the least significant 32 bits of the cycle counter's
CYCLES
64-bit count value. The most significant 32 bits are contained by
CYCLES2.
21-24 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
CYCLES
The most significant 32 bits (MSBs) are
CYCLES.
.
value in a shadow register, and all subsequent reads of
come from the shadow register. The shadow register is
and . The least significant 32
CYCLES2
stores the current
CYCLES
.
CYCLES
bit in the
CCEN SYSCFG
and
CYCLES CYCLES2
CCLK
register. The
) are shown in
cycle. The