L1 Data Memory; Dmem_Control Register - Analog Devices ADSP-BF53x Blackfin Reference

L1 Data Memory

L1 Data Memory
The L1 data SRAM/cache is constructed from single-ported subsections,
but organized to reduce the likelihood of access collisions. This organiza-
tion results in apparent multi-ported behavior. When there are no
collisions, this L1 data traffic could occur in a single core clock cycle:
• Two 32-bit data loads
• One pipelined 32-bit data store
• One DMA I/O, up to 64 bits
• One 64-bit cache fill/victim access
L1 Data Memory can be used only to store data.

DMEM_CONTROL Register

The Data Memory Control register (
for the L1 Data Memory.
The
PORT_PREF1
non-cacheable L2 fetches. Cacheable fetches are always processed by the
data port physically associated with the targeted cache memory. Steering
DAG0, DAG1, and cache traffic to different ports optimizes performance
by keeping the queue to L2 memory full.
6-24 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
bit selects the data port used to process DAG1
) contains control bits
DMEM_CONTROL