Special SIMD Video ALU Operations
Four 8-bit Video ALUs enable the processor to process video information
with high efficiency. Each Video ALU instruction may take from one to
four pairs of 8-bit inputs and return one to four 8-bit results. The inputs
are presented to the Video ALUs in two 32-bit words from the Data Reg-
ister File. The possible operations include:
• Quad 8-Bit Add or Subtract
• Quad 8-Bit Average
• Quad 8-Bit Pack or Unpack
• Quad 8-Bit Subtract-Absolute-Accumulate
• Byte Align
For more information about the operation of these instructions, see
ter 18, "Video Pixel Operations."
Multiply Accumulators (Multipliers)
The two multipliers (MAC0 and MAC1) perform fixed-point multiplica-
tion and multiply and accumulate operations. Multiply and accumulate
operations are available with either cumulative addition or cumulative
subtraction.
Multiplier fixed-point instructions operate on 16-bit fixed-point data and
produce 32-bit results that may be added or subtracted from a 40-bit
accumulator.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Computational Units
Chap-
2-35