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DCPLB_DATAx Registers
Figure 6-20
shows the DCPLB Data registers (
To ensure proper behavior and future compatibility, all reserved
bits in this register must be set to 0 whenever this register is
written.
DCPLB Data Registers (DCPLB_DATAx)
For Memory-
mapped
addresses, see
Table
6-3.
CPLB_L1_AOW
Valid only if write
through cacheable
(CPLB_VALID = 1,
CPLB_WT = 1)
0 - Allocate cache lines
on reads only
1 - Allocate cache lines
on reads and writes
CPLB_WT
Operates only in cache mode
0 - Write back
1 - Write through
CPLB_L1_CHBL
Clear this bit when L1 memory is
configured as SRAM
0 - Non-cacheable in L1
1 - Cacheable in L1
CPLB_DIRTY
Valid only if write back cacheable (CPLB_VALID = 1,
CPLB_WT = 0, and CPLB_L1_CHBL = 1)
0 - Clean
1 - Dirty
A protection violation exception is generated on store
accesses to this page when this bit is 0. The state of
this bit is modified only by writes to this register. The
exception service routine must set this bit.
Figure 6-20. DCPLB Data Registers
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
DCPLB_DATAx
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Memory
).
Reset = 0x0000 0000
PAGE_SIZE[1:0]
00 - 1K byte page size
01 - 4K byte page size
10 - 1M byte page size
11 - 4M byte page size
CPLB_VALID
0 - Invalid (disabled) CPLB entry
1 - Valid (enabled) CPLB entry
CPLB_LOCK
Can be used by software in
CPLB replacement algorithms
0 - Unlocked, CPLB entry can
be replaced
1 - Locked, CPLB entry should
not be replaced
CPLB_USER_RD
0 - User mode read access
generates protection
violation exception
1 - User mode read access
permitted
CPLB_USER_WR
0 - User mode write access
generates protection
violation exception
1 - User mode write access
permitted
CPLB_SUPV_WR
0 - Supervisor mode write
access generates protection
violation exception
1 - Supervisor mode write
access permitted
6-57
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