Examples Of Protected Memory Regions - Analog Devices ADSP-BF53x Blackfin Reference

Memory Protection and Properties

Examples of Protected Memory Regions

In Figure 6-18, a starting point is provided for basic CPLB allocation for
Instruction and Data CPLBs. Note some ICPLBs and DCPLBs have com-
mon descriptors for the same address space.
Figure 6-18. Examples of Protected Memory Regions
6-54 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
INSTRUCTION CPLB SETUP
L1 INSTRUCTION: SRAM
NON-CACHEABLE 1MB PAGE
DATA CPLB SETUP
L1 DATA: SRAM
NON-CACHEABLE ONE 4MB PAGE
SDRAM: CACHEABLE
EIGHT 4MB PAGES
ASYNC: NON-CACHEABLE
ONE 1MB PAGE
ASYNC: CACHEABLE
TWO 1MB PAGES
SDRAM: CACHEABLE
EIGHT 4MB PAGES
ASYNC: NON-CACHEABLE
ONE 1MB PAGE
ASYNC: CACHEABLE
ONE 1MB PAGE