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Introduction
Table 4-1. Non-memory-mapped Sequencer Registers
Register Name
SEQSTAT
RETX
RETN
RETI
RETE
RETS
LC0, LC1
LT0, LT1
LB0, LB1
FP, SP
SYSCFG
CYCLES, CYCLES2
PC
In addition to these central sequencer registers, there is a set of mem-
ory-mapped registers that interact closely with the program sequencer. For
information about the interrupt control registers, see
rupts" on page
are memory-mapped, they still connect to the same 32-bit Register Access
Bus (RAB) and perform in the same way. Registers of the System Interrupt
Controller connect to the Peripheral Access Bus (PAB) which resides in
the
domain. On some derivatives the PAB bus is 16 bits wide; on
SCLK
others it is 32 bits wide. For debug and test registers see
"Debug."
4-6
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
Sequencer Status register: See
Exception Handling" on page
Return Address registers: See
on page
Exception Return
NMI Return
Interrupt Return
Emulation Return
Subroutine Return
Zero-Overhead Loop registers: See
on page
Loop Counters
Loop Tops
Loop Bottoms
Frame Pointer and Stack Pointer: See
Pointers" on page 5-6
System Configuration register: See
on page 21-26
Cycle Counters: See
ters" on page 21-24
Program Counter. The PC is an embedded register. It is
not directly accessible with program instructions.
4-29. Although the registers of the Core Event Controller
"Hardware Errors and
4-58.
"Events and Interrupts"
4-29.
4-21.:
"CYCLES and CYCLES2 Regis-
"Events and Inter-
Chapter 21,
"Hardware Loops"
"Frame and Stack
"SYSCFG Register"
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