Logical Shift - Analog Devices ADSP-BF53x Blackfin Reference

r3.l = r0.h >>> 7(s) ;
saturated */
r4 = r2 >>> 20 ;
A0 = A0 >>> 1 ;
r0 >>>= r2 ;
shift */
r3.l = r0.h << 12 (S) ;
r5 = r2 << 24(S) ;
r3.l = ashift r0.h by r7.l ;
r3.h = ashift r0.l by r7.l ;
r3.h = ashift r0.h by r7.l ;
r3.l = ashift r0.l by r7.l ;
r3.l = ashift r0.h by r7.l(s) ;
saturated */
r3.h = ashift r0.l by r7.l(s) ;
saturated */
r3.h = ashift r0.h by r7.l(s) ;
r3.l = ashift r0.l by r7.l (s) ;
r4 = ashift r2 by r7.l ;
r4 = ashift r2 by r7.l (s) ;
A0 = ashift A0 by r7.l ;
A1 = ashift A1 by r7.l ;
// If r0.h = -64, then performing . . .
r3.h = r0.h >>> 4 ;
sign */
Also See
Vector Arithmetic
Add, ROT (Rotate)
Special Applications
Multiply, divide, and normalize signed numbers
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* arithmetic right shift, half-word,
/* arithmetic right shift, word */
/* arithmetic right shift, Accumulator */
/* 16-bit instruction length arithmetic right
/* arithmetic left shift */
/* arithmetic left shift */
/* shift, word */
/* shift, Accumulator */
/* shift, Accumulator */
/* . . . produces r3.h = -4, preserving the
Shift, Vector Logical
Shift/Rotate Operations
/* shift, half-word */
/* shift, half-word,
/* shift, half-word,
/* shift, word, saturated */
Shift, Logical Shift, Shift with
14-13