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Table C-21. Vector Operations Instructions (Sheet 11 of 33)
Instruction
and Version
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IH)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (M)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (FU, M)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IS, M)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IU, M)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (T, M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0
0xC364 2000—
0xC364 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0
0xC214 2000—
0xC214 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0
0xC294 2000—
0xC294 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0
0xC314 2000—
0xC314 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 1 0 0 1 0 1 0 0
0xC394 2000—
0xC394 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0
0xC254 2000—
0xC254 E7FF
Dreg
half 1 1 0 0
Instruction Opcodes
Bin
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-117
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