Analog Devices ADSP-BF53x Blackfin Reference page 1029

overflow
bits, 2-14
flags (AV0,AV1), 2-14
impossible in the multiply 32-bit
operands instruction,
prevention in divide primitive
instruction, 15-22
saturation of multiplier results,
user-implemented for multiply 32-bit
operands instruction,
P
PAB (peripheral access bus),
packing instructions
quad 8-bit unpack, C-106
vector pack, 19-48, C-138
PACK (vector pack) instruction, 19-48,
C-138
page descriptor table, 6-53
PAGE_SIZE[1:0] field, 6-55,
parallel instructions
issuing, 20-1
syntax, 20-2
parameter passing, 4-15
patch registers, B-8
pattern_reg bit field extraction instruction,
13-16
PC (program counter) register
non-memory mapped,
pcrel11m2, 7-6
pcrel13m2, 7-2
pcrel25m2, 7-3, 7-8
pcrel5m2, 7-14
PC-relative
constant, 1-12, C-6
offset, 4-11, 4-12
pcrelm2, 7-2
PEMUSWx bits, 21-20,
pending event requests, coordinating,
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
15-51
2-38
15-51
6-73
6-57
4-6
21-21
4-38
performance monitor control (PFCTL)
register, 21-19, 21-20
performance monitor counter (PFCNTRn)
registers, 21-19, 21-20
performance monitor registers,
performance monitor unit,
peripheral
interrupt generated by,
interrupts, 4-30
interrupts, relative priority,
interrupts, source masking,
interrupt sources, 4-35
supporting interrupts,
waking up core, 4-34
peripheral access bus (PAB),
PFCEN0[1:0] field, 21-21
PFCEN1[1:0] field, 21-21
PFCNT0 bit, 21-21
PFCNT1 bit, 21-21
PFCNTRn (performance monitor counter)
register, 21-20
PFCNTRn (performance monitor counter)
registers, 21-19
PFCTL (performance monitor control)
register, 21-19, 21-20
PFMON0[7:0] field, 21-21
PFMON1[7:0] field, 21-21
PFPWR bit, 21-21
pipeline
figure, 4-8
instruction, 4-3, 4-7
instructions when interrupt occurs,
interlocked, 6-66
stages, 4-7
stalls, 6-66
pointer register file, 2-6
pointer register modification,
pointer registers (P[5:0])
defined, 5-6
description, 1-13
Index
B-9
21-19
4-31
4-37
4-36
4-33
6-73
4-67
5-15
I-27