Analog Devices ADSP-BF53x Blackfin Reference page 980

Instructions Listed By Operation Code
Table C-23. 32-Bit Opcode Instructions (Sheet 27 of 40)
Instruction
and Version
Negate (Two's-Complement)
A1 = – A1, A0 = – A0
Vector Negate (Two's-Complement)
Dreg = – Dreg (V)
Absolute Value
A0 = ABS A0
Absolute Value
A0 = ABS A1
Absolute Value
A1 = ABS A1, A0 = ABS A0
Vector Add / Subtract
Dreg = A1 + A0, Dreg = A1 – A0
Vector Add / Subtract
Dreg = A1 + A0, Dreg = A1 – A0 (S)
Vector Add / Subtract
Dreg = A0 + A1, Dreg = A0 – A1
Vector Add / Subtract
Dreg = A0 + A1, Dreg = A0 – A1 (S)
Quad 8-Bit Subtract-Absolute-Accumulate
SAA (Dreg_pair, Dreg_pair)
Quad 8-Bit Subtract-Absolute-Accumulate
SAA (Dreg_pair, Dreg_pair) (R)
Disable Alignment Exception for Load
DISALGNEXCPT
Quad 8-Bit Average-Byte
Dreg = BYTEOP1P (Dreg_pair, Dreg_pair)
Quad 8-Bit Average-Byte
Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (R)
Quad 8-Bit Average-Byte
Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T)
Quad 8-Bit Average-Byte
Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T, R)
C-180 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
0xC40E C03F
0xC40F C000—
0xC40F CE38
0xC410 0000
0xC410 403F
0xC410 C03F
0xC411 003F—
0xC411 0FC0
0xC411 203F—
0xC411 2FC0
0xC411 403F—
0xC411 4FC0
0xC411 603F—
0xC411 6FC0
0xC412 0000—
0xC412 003F
0xC412 2000—
0xC412 203F
0xC412 C000
0xC414 0000—
0xC414 0E3F
0xC414 2000—
0xC414 2E3F
0xC414 4000—
0xC414 4E3F
0xC414 6000—
0xC414 6E3F