Analog Devices ADSP-BF53x Blackfin Reference page 647

Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
Example
disalgnexcpt || r1 = [i0++] || r3 = [i1++] ;
tions in parallel */
disalgnexcpt || [p0 ++ p1] = r5 || r3 = [i1++] ;
exception is prevented only for the load */
disalgnexcpt || r0 = [p2++] || r3 = [i1++] ;
exception is prevented only for the I-reg load */
Also See
Any Quad 8-Bit instructions,
Special Applications
Use the
DISALGNEXCPT
8-Bit single-instruction, multiple-data (SIMD) instructions.
Quad 8-Bit SIMD instructions require as many as sixteen 8-bit operands,
four D-registers worth, to be preloaded with operand data. The operand
data is 8 bits and not necessarily word aligned in memory. Thus, use
to prevent spurious exceptions for these potentially misaligned
ALGNEXCPT
accesses.
During execution, when Quad 8-Bit SIMD instructions perform 8-bit
boundary accesses, they automatically prevent exceptions for misaligned
accesses. No user intervention is required.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
"Issuing Parallel Instructions" on page
ALIGN8, ALIGN16, ALIGN24
instruction when priming data registers for Quad
Video Pixel Operations
/* three instruc-
/* alignment
/* alignment
20-1.
DIS-
18-7