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Memory Protection and Properties
INSTRUCTION ALIGNMENT UNIT
E
F
G
INSTRUCTION ALIGNMENT UNIT
T+10 A EXECUTES
T+18 E EXECUTES
E
F
G
INSTRUCTION ALIGNMENT UNIT
Figure 6-17. L2 Latency With Cache Off
The MMU is implemented as two 16-entry Content Addressable Memory
(CAM) blocks. Each entry is referred to as a Cacheability Protection
Lookaside Buffer (CPLB) descriptor. When enabled, every valid entry in
the MMU is examined on any fetch, load, or store operation to determine
whether there is a match between the address being requested and the page
described by the CPLB entry. If a match occurs, the cacheability and pro-
tection attributes contained in the descriptor are used for the memory
transaction with no additional cycles added to the execution of the
instruction.
Because the L1 memories are separated into instruction and data memo-
ries, the CPLB entries are also divided between instruction and data
CPLBs. Sixteen CPLB entries are used for instruction fetch requests; these
are called ICPLBs. Another sixteen CPLB entries are used for data transac-
tions; these are called DCPLBs. The ICPLBs and DCPLBs are enabled by
setting the appropriate bits in the L1 Instruction Memory Control
6-46
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
A
B
C
D
H
A
B
C
D
T+11 B EXECUTES
T+12 C EXECUTES
T+13 D EXECUTES
H
I
J
K
L
A
E
T+9 ABCD READY
L2 MEMORY
TO EXECUTE
I
EACH INSTRUCTION FETCH IS 64 BITS
64 BITS
T
CYCLES
B
C
D
F
G
H
J
K
L
T+9
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