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L1 Instruction Memory
Cache Line Fills
A cache line fill consists of fetching 32 bytes of data from memory. The
operation starts when the instruction memory unit requests a line-read
data transfer on its external read-data port. This is a burst of four 64-bit
words of data from the line fill buffer. The line fill buffer translates then
to the bus width of the External Access Bus (EAB).
The address for the read transfer is the address of the target instruction
word. When responding to a line-read request from the instruction mem-
ory unit, the external memory returns the target instruction word first.
After it has returned the target instruction word, the next three words are
fetched in sequential address order. This fetch wraps around if necessary,
as shown in
Table
Table 6-1. Cache Line Word Fetching Order
Target Word
WD0
WD1
WD2
WD3
Once the line fill has completed, the four 64-bit words have fixed order in
the cache as shown in
bits (byte select) of the address word along with the cache entry.
6-14
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
6-1.
Fetching Order for Next Three Words
WD0, WD1, WD2, WD3
WD1, WD2, WD3, WD0
WD2, WD3, WD0, WD1
WD3, WD0, WD1, WD2
Figure
6-4. This avoids the need to save the lower 5
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