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the Invalid bit of each cache line to the invalid state. To implement this
technique, additional MMRs (
available to allow arbitrary read/write of all the cache entries directly. This
method is explained in the next section.
For invalidating the complete instruction cache, a third method is avail-
able. By clearing the
"L1 Instruction Memory Control Register," on page
the instruction cache are set to the invalid state. A second write to the
IMEM_CONTROL
as cache again. An
cache and a
CSYNC
operations.
Instruction Test Registers
The Instruction Test registers allow arbitrary read/write of all L1 cache
entries directly. They make it possible to initialize the instruction tag and
data arrays and to provide a mechanism for instruction cache test, initial-
ization, and debug.
When the Instruction Test Command register (
the L1 cache data or tag arrays are accessed, and data is transferred
through the Instruction Test Data registers (
registers contain either the 64-bit data that the access is to
ITEST_DATAx
write to or the 64-bit data that was read during the access. The lower 32
bits are stored in the
stored in the
ITEST_DATA[1]
ITEST_DATA[0]
begin with
Figure 6-6 on page
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
ITEST_COMMAND
bit in the
IMC
register to set the
IMC
instruction should be run before invalidating the
SSYNC
instruction should be inserted after each of these
ITEST_DATA[0]
register. When the tag arrays are accessed,
is used. Graphical representations of the
6-21.
and
ITEST_DATA[1:0]
register (see
IMEM_CONTROL
6-7), all Valid bits in
bit configures the instruction memory
ITEST_COMMAND)
ITEST_DATA[1:0])
register, and the upper 32 bits are
Memory
) are
Figure 6-2,
is used,
. The
registers
ITEST
6-19
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