Vector Logical Shift - Analog Devices ADSP-BF53x Blackfin Reference

Instruction Overview

Vector Logical Shift

General Form
dest_reg = src_reg >> shift_magnitude (V)
dest_reg = src_reg << shift_magnitude (V)
dest_reg = LSHIFT src_reg BY shift_magnitude (V)
Syntax
Constant Shift Magnitude
Dreg = Dreg >> uimm4 (V) ;
(b) */
Dreg = Dreg << uimm4 (V) ;
(b) */
Registered Shift Magnitude
Dreg = LSHIFT Dreg BY Dreg_lo (V) ;
Syntax Terminology
:
Dreg R7–0
:
Dreg_lo R7–0.L
: unsigned 4-bit field, with a range of 0 through 15
uimm4
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Vector Logical Shift logically shifts a pair of half-word registered
numbers a specified distance and direction. Though the two half-word
registers are shifted at the same time, the two numbers are kept separate.
19-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* logical shift right, immediate
/* logical shift left, immediate
/* logical shift (b) */