Analog Devices ADSP-BF53x Blackfin Reference page 505

Example
p3 = p2 >> 1 ;
p3 = p3 >> 2 ;
p4 = p5 << 1 ;
p0 = p1 << 2 ;
r3 >>= 17 ;
r3 <<= 17 ;
r3.l = r0.l >> 4 ;
r3.l = r0.h >> 4 ;
nations are arbitrary */
r3.h = r0.l << 12 ;
r3.h = r0.h << 14 ;
binations are arbitrary */
r3 = r6 >> 4 ;
r3 = r6 << 4 ;
a0 = a0 >> 7 ;
a1 = a1 >> 25 ;
a0 = a0 << 7 ;
a1 = a1 << 14 ;
r3 >>= r0 ;
r3 <<= r1 ;
r3.l = lshift r0.l by r2.l ;
sign of R2.L */
r3.h = lshift r0.l by r2.l ;
a0 = lshift a0 by r7.l ;
a1 = lshift a1 by r7.l ;
/* If r0.h = -64 (or 0xFFC0), then performing . . . */
r3.h = r0.h >> 4 ;
losing the sign */
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* pointer right shift by 1 */
/* pointer right shift by 2 */
/* pointer left shift by 1 */
/* pointer left shift by 2 */
/* data right shift */
/* data left shift */
/* data right shift, half-word register */
/* same as above; half-word register combi-
/* data left shift, half-word register */
/* same as above; half-word register com-
/* right shift, 32-bit word */
/* left shift, 32-bit word */
/* Accumulator right shift */
/* Accumulator right shift */
/* Accumulator left shift */
/* Accumulator left shift */
/* data right shift */
/* data left shift */
/* . . . produces r3.h = 0x0FFC (or 4092),
Shift/Rotate Operations
/* shift direction controlled by
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