System Peripheral Interrupts - Analog Devices ADSP-BF53x Blackfin Reference

"INTERRUPT
A"
PERIPHERAL
INTERRUPT
REQUESTS
SYSTEM
WAKEUP
(SIC_IWR) (SIC_ISR)
TO DYNAMIC POWER
MANAGEMENT
CONTROLLER
SYSTEM INTERRUPT CONTROLLER
NOTE: NAMES IN PARENTHESES ARE MEMORY-MAPPED REGISTERS.
Figure 4-4. Interrupt Processing Block Diagram

System Peripheral Interrupts

The processor system has numerous peripherals, which therefore require
many supporting interrupts.
The peripheral interrupt structure of the processor is flexible. By default
upon reset, multiple peripheral interrupts share a single, general-purpose
interrupt in the core, as shown in the System Interrupt Appendix of the
Blackfin Processor Hardware Reference for your part.
An interrupt service routine that supports multiple interrupt sources must
interrogate the appropriate system memory mapped registers (MMRs) to
determine which peripheral generated the interrupt.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
SYSTEM ASSIGN
INTERRUPT SYSTEM
MASK PRIORITY
(SIC_IMASK) (SIC_IARx)
SYSTEM
STATUS
Program Sequencer
EMU
RESET
NMI
EVX
IVTMR
IVHW
CORE
CORE
INTERRUPT
STATUS
MASK
(ILAT)
(IMASK)
CORE EVENT CONTROLLER
CORE
EVENT
VECTOR
TABLE
(EVT[15:0])
CORE
PENDING
(IPEND)
4-33